Embodiments of the present disclosure relate to a sense-amplifier driving device and a semiconductor device including the same.
With increases in the degree of integration of semiconductor memory devices, the operation speed of semiconductor memory devices has also been continuously improved. In order to increase the operation speed of a semiconductor memory device, a synchronous memory device operating in synchronization with an external clock has been proposed and developed.
A representative synchronous memory device is a single data rate (SDR) synchronous memory device, which is synchronized with a rising edge of an external clock such that one piece of data is input or output via one data pin during one cycle of the external clock.
However, the ability of an SDR synchronous memory device to satisfy the demands of a high-speed operation of a system is limited. In order to solve the problem of the SDR synchronous memory device, a double data rate (DDR) synchronous memory device capable of processing two pieces of data during one clock cycle has been proposed.
In a DDR synchronous memory device, two contiguous pieces of data are input or output via respective data input/output (I/O) pins, and the two contiguous pieces of data are synchronized with a rising edge and a falling edge of an external clock, respectively. Therefore, although the clock frequency of a DDR synchronous memory device does not increase, the DDR synchronous memory device has a bandwidth that is at least two times larger than that of a SDR synchronous memory device. As a result, a DDR synchronous memory device can operate at a higher speed than a SDR synchronous memory device.
A dynamic random access memory (DRAM) is a representative volatile memory. A memory cell of the DRAM includes one cell transistor and one cell capacitor. The cell transistor controls access to the cell capacitor, and the cell capacitor stores electric charges corresponding to data. Data stored in the cell capacitor is classified into high-level data and low-level data according to the amount of electric charges stored in the cell capacitor.
Since electric charges are applied to or leak out from the cell capacitor of the memory cell of the DRAM by a leakage component, the corresponding data should be periodically re-written into the cell capacitor. The periodic storing operation for maintaining desired data in the memory cell is referred to as a ‘refresh’ operation.
A memory cell of a DRAM is activated in an active mode. A bit-line sense-amplifier (sense-amp) circuit senses and amplifies data received from the activated memory cell, and re-transmits the amplified data to the memory cell. After that, the memory cell is deactivated in a precharge mode and maintains data stored therein. The refresh operation is performed by repeatedly performing active and precharge operations at intervals of a predetermined time.
However, as the voltage level of an external power-supply voltage VDD decreases, as indicated in the LPDDR4 specification of a DRAM, a core voltage Vcore having a lower voltage level than the power-supply voltage VDD is used as an internal voltage, resulting in reduction of the data retention time of a memory cell. Therefore, refresh characteristics of a DRAM are gradually deteriorated in proportion to the voltage level of the external power-supply voltage VDD when the DRAM operates at a high speed.